10 bit 100 MSps pipeline ADC for video and SDR The Challenge To develop an ADC core that could be embedded onto digital video processing ASICs to enable our long-standing customer to better control content and quality. At this time - in 2004 - only a very limited number of IP providers could provide solutions for ADC applications. The solution A dedicated ADC core to optimize area and power - the different pipeline stages were scaled.  To assure linearity performance at high frequencies, a dedicated on-chip Sample & Hold topology was implemented. Result for the customer The core complements and completes our customer’s ASIC offering. It enables him to supply a fully integrated video processing chip that includes video ADC and provides him with a competitive leverage.

Applications Video and SDR Key baseline features 10bit @ 100MSps 9.2 ENOB @ 16 MHz input signal Input range: 1.2V differential ptp Analog Bandwidth > 250MHz Area < 1.5 mm2 Power < 120mW @ 1.2V supply TSMC 0.13 µm CMOS