AnSem - Innovation on chip

Programmable Multi-standard home networking AFE

Programmable Multi-standard home networking AFE
Programmable Multi-standard home networking AFE

The real world problem

The rapid worldwide proliferation of personal computers and the internet in homes, advancements in telecommunications technology, and progress in the development of smart devices have increasingly emphasized the last few hundred feet of any consumer-related network.

Distributing entertainment data over existing coax cable, phone lines and power lines has become the center piece of home networking evolution. Various Home Networking technologies enable service providers to drive the growing demand for new multimedia services such as IPTV and VoIP to the home and small offices, with guaranteed Quality of Service over the existing wiring.

Kawasaki Micro-Electronics (K-micro) is a Japanese company specialized in ASIC technologies for consumer electronics and networking and storage markets. They are member of industry standardization organizations like ITU,, PLC, P1901, HomePlug and HomePNA.  As a pioneer company, K-micro developed an ASIC for multi-standard usage targeting, PLC and HomePNA applications enabling data rates up to 1Gb/s over existing power and coax lines. This state-of-the-art ASIC is currently used worldwide by large players in the telecom market and consumer market.

The solution

K-micro and AnSem have a tradition of successful collaboration leading to several chip developments for SerDes and HomePNA.  For this ASIC, K-micro contracted AnSem for the development of critical analog circuits as the multi-standard programmability elevated the specifications of the analog functionality.

In particular, the architectural design phase revealed that a 400Msps 12-bit DAC was required to meet the full performance and hence the data rate of 1Gbps.  A full MATLAB™ model of this block was built by AnSem to investigate the impact of non-idealities and set specifications of all sub-blocks. This resulted in a programmable current-steering DAC with back-ground calibration to allow for high-accuracy while enabling different transmit powers.

At the receive side, a time-interleaved 320Msps 12-bit pipelined ADC was integrated using existing IP preceded by  a wide-range programmable gain amplifier (PGA)  and a high bandwidth filter.

Filter bandwidth is typically programmable over a wide frequency range to support different types of interconnect and legacy bandwidths. Achieving a high SNR, having both low noise and an excellent linearity at the same time, is the key requirement for these filter/PGA combinations to achieve the highest possible data throughput. Modulation constellations up to QAM1024 are achieved. The implemented filter bandwidth for is 90MHz, the implemented noise level is below 3nV/vHz.

Both data converters and the interface towards the digital back-end were driven by a low-noise PLL using CML logic to generate all clocks for the different ASIC operation modes.  All circuitry was developed in standard 130nm CMOS operating over temperatures between -50°C to +125°C.

Key technical statistics

  • 12-bit 320Msps pipelined ADC featuring down-sampling FIR filter
  • 12-bit 400Msps DAC featuring up-sampling FIR filter to ease TX filtering requirements with programmable output power up to 12dBm.
  • High linear, low-noise VGA including offset calibration and programmable filtering
  • Synthesizer with 3.2GHz VCO and CML dividers to generate low-jitter clocks from 50Msps to 400Msps.