DECT Synthesizer The Challenge In 1999, forced by the cost driven nature of the consumer telecommunications market, AnSem’s customer - an important player in the DECT market, needed to strengthen his position by complementing his baseband chip with a more cost-effective CMOS front-end chip. AnSem’s brief was to develop an alternative DECT synthesizer design that provided significant cost and area reduction. This required an RF CMOS circuit design above 3 GHz. The solution A custom made DECT synthesizer running at a double frequency rate, using an LC-VCO at 3.8 GHz. A 3.8 GHz CML divide-by-2 was used to reduce quadrature generation complexity. Significant power saving in the prescaler was achieved by using TSPC logic up to 1.9 GHz. Result for the customer Reduced production costs. Experience in RF CMOS design due to the close collaboration with AnSem. Relatively low risk and short time to market, since the critical work was outsourced to a ‘specialist company’.

Application DECT market Key baseline features 0.25µm CMOS technology Prescaler, PLL on chip  Fully balanced VCO with integrated varactor diodes and inductor Dedicated high-speed digital logic  Tuning range from 1.65 to 2.10GHz  Phase noise < -117dBc @ 1MHz