0.13 µm XAUI/SONET 2.5-3.125 Gbps SerDes
The Challenge
In 1999, advanced SerDes technology was mainly implemented in stand-alone bipolar ASSPs. With the advent of 0.13 µm CMOS technology, there started a strong move to embed SerDes technology into large digital ASICs.
Our customer - a major player in the ASIC market - identified very early - on that access to SerDes technology was a key factor to his continued leadership. He also realized that an in-depth understanding of both low jitter (low phase noise) PLL integration and very high speed logic integration, with low noise sensitivity, was a prerequisite to achieving this.
Our customer tapped into AnSem’s long history of RF CMOS expertise, challenging us to develop a high-speed datacommunication SerDes.
The solution
A multi-core, multi-rate SerDes PHY in 0.13 µm CMOS that achieves very low jitter by using an optimized LC-VCO for TX data generation.
RX is achieved with a bang-bang digital loop filter CDR topology, allowing for complex jitter tracking characteristics.
Result for the customer
- Early access to high-speed SerDes technology.
- Silicon proven SerDes core allowing application specific ASIC optimizations.
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SerDes technology
Serial communication can be enabled using SerDes (Serializer/Deserializer) systems, in which parallel data is serialized at the transmit end. At the receiver end, the clock and data are recovered from the high-speed serial data, after which it can be de-serialized. |
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