0.13 µm SONET OC192 10 Gbps SerDes The Challenge In 2003, AnSem was challenged to develop an ultra fast 10 Gbps SerDes PHY in 0.13µm technology. Our customer wished to reinforce his technological  leadership and to factor into his roadmap a 10 Gbps SerDes. The solution needed to be: flexible, robust and reliable easily ported to different specifications capable of meeting future data rate transfers The project focus was the development of new core technology. The solution A 10 Gbps SerDes macro-cell capable of  performing over a 24-inch backplane.  A dedicated architecture, optimized for very high speed operation, was selected using LC-VCO for TX and a direct bang-bang modulation of a ring-oscillator VCO for RX CDR. Result for the customer New technology was delivered to our customer, enabling him to prepare for future SerDes market demands, and providing proof of  his technological readiness to potential customers.

Key baseline features High speed architecture: Ring oscillator for high speed CDR LC oscillator for low jitter serializer Data rates of up to 10 Gbps Half rate clock TSMC 0.13 µm standard CMOS Multi standard operation Jitter optimized: Ring oscillator for Rx channels LC oscillator for Tx Transmitter jitter < 0.1 UI Receiver jitter tolerance >0.6 UI Power consumption: 330 mW