10 bit 100MSps pipeline ADC for video and SDR

  • Consumer
  • Sensors & MEMS Data Aqcuisition

AnSem · 10 bit 100MSps pipeline ADC for video and SDR

The real world problem

In 2004 only a very limited number of IP vendors could provide video rate ADC solutions for applications such as digital video processing. Our long-standing Analog ASIC customer needed such an ADC for their digital video processing engine ASIC. More importantly they needed a trustworthy partner to enable them to control both the specification and quality of the embedded block.

The solution

The customer's ASIC was based on the standard TSMC 0.13µm CMOS. AnSem was asked to design the dedicated pipelined 10bit @ 100MSps ADC core because we had consistently exceeded the customer's expectations in previous projects. To optimize area and power AnSem used a 1.2V power supply and carefully scaled the different pipeline stages. To assure linearity performance at high frequencies a dedicated on-chip Sample & Hold topology was implemented and the differential analog front end was designed to have more than 250MHz bandwidth.

Result for the customer

The ADC complemented and completed our customer's ASIC offering. It enabled him to supply a fully integrated video processing chip that included video ADC which provided competitive leverage versus competing devices.

Key technical statistics

  • 9.2 ENOB @ 16 MHz input signal
  • Area < 1.5 mm2
  • Power < 120mW @ 1.2V supply